Field of the Invention
The invention disclosed in this specification relates to a data holding device, a nonvolatile data holding device, and a data reading method.
Description of Related Art
FIG. 22 is a circuit diagram showing a conventional example of a data holding device (corresponding to FIG. 1 of JP-A-2016-58120 filed by the present applicant). A data holding device 3b of this conventional example includes a data holding portion M, a ferroelectric storing portion K, and a sense amplifier SA, and it functions as a nonvolatile latch capable of holding (latching), saving (storing), and restoring (recalling) a data signal Din responding to various signals from a control unit 3a. 
However, in the data holding device 3b of FIG. 22, an inverter loop (NAND loop) of the data holding portion M and an inverter loop (not shown) of the sense amplifier SA are overlapped, and there is room for further improvement in reduction of circuit scale.
From another point of view, the conventional sense amplifier SA uses the inverter loop for only sensing function (i.e. a function of fixing a logic level of an output signal according to an input signal), and there is room for further study about utilizing the inverter loop.
Note that also in a sense amplifier incorporated in a semiconductor memory other than a nonvolatile latch or a nonvolatile flip-flop (e.g. a ferroelectric random access memory (FeRAM), a static RAM (SRAM), a dynamic RAM (DRAM) or the like), the inverter loop is dedicated for sensing, and there was no idea of utilizing the inverter loop for other use.
In addition, FIG. 55 is a circuit diagram showing a conventional example of a nonvolatile data holding device (corresponding to FIG. 15 of Japanese Patent No. 5421779 filed by the present applicant). The nonvolatile data holding device of this conventional example includes a loop structure LOOP that holds an input data signal D, and ferroelectric elements (CL1xa, CL1xb, CL2xa, and CL2xb) (x=1, 2, . . . m) that store m-bit (m≥2) data signal D in a nonvolatile manner.
However, the nonvolatile data holding device of FIG. 55 includes only transistors (Q1xa, Q1xb, Q2xa, and Q2xb) that short-circuit both terminals of the individual ferroelectric elements as data protection means thereof, and there is room for further improvement in reliability of data protection.
In addition, FIG. 64 is a circuit diagram showing a conventional example of a nonvolatile data holding device (corresponding to FIG. 26 of Japanese Patent No. 5514574 filed by the present applicant). The nonvolatile data holding device of this conventional example includes a nonvolatile storing portion NVM that stores the data signal D in a nonvolatile manner by using hysteresis characteristics of the ferroelectric elements.
Note that when the data signal D is written in the nonvolatile storing portion NVM, complementary data are written to the ferroelectric elements CL1a and CL1b, and to the ferroelectric elements CL2a and CL2b. On the other hand, when the data signal D is read from the nonvolatile storing portion NVM, input signals SDnC and SDC corresponding to the complementary data described above are generated using capacitive coupling between the ferroelectric elements CL1a and CL1b, and capacitive coupling between the ferroelectric elements CL2a and CL2b, and a logic level of the data signal D is determined based on a magnitude relationship between them.
However, in the nonvolatile data holding device of FIG. 64, if the capacitive-coupled ferroelectric elements have different effective areas due to a variation in manufacturing process, then offset fluctuation of the input signals SDnC and SDC occurs, which may cause a reduction in operation margin when reading data.
In particular, because offset fluctuations of the input signals SDnC and SDC due to effective area variation of the ferroelectric elements are large in the conventional data reading method, the operation margin when reading data may not be sufficiently secured, and there is room for further improvement.